OBRARY

TECHNICAL REPORT SECTION NAVAL POSTGRADUATE SCHOO MONTEREY. CALI OPNIA 9394C

NPS62-79-015PR

RMTPD3TGRADUATE SCHOOL

Monterey, California

Analog-to-Digital Signal Processing in a Prototype SATCOM Signal Analyzer

John E. Ohlson William B. Zell, Jr.

December 1979 Project Report

FEDDOCS

D 208.14/2:NPS-62-79-015PR

^proved for public release; distribution unlimited

repared for: Naval Electronic Systems Command PME-106-1 Washington, D.C. 20360

NAVAL POSTGRADUATE SCHOOL Monterey, California

Rear Admiral T. F. Dedman Jack R. Bosting

Superintendent Provost

The work reported herein was supported in part by the Naval Electronic Systems Command, PME-106-1.

Reproduction of all or part of this report is authorized.

This report was prepared by:

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t. REPORT NUMBER

NPS62-79-015PR

2. GOVT ACCESSION NO

3. RECIPIENT'S CATALOG NUMBER

4. TITLE (and Subtitle)

Analog-to-Digital Signal Processing in a Prototype SATCOM Signal Analyzer

5. TYPE OF REPORT St PERIOD COVERED

Project Report

6. PERFORMING ORG. REPORT NUMBER

7. AUTHORfsJ

John E. Ohlson William B. Zell, Jr.

8. CONTRACT OR GRANT NUMBERS.)

9. PERFORMING ORGANIZATION NAME AND ADDRESS

Naval Postgraduate School Monterey, California 93940

10. PROGRAM ELEMENT. PROJECT. TASK AREA 4 WORK UNIT NUMBERS

N0003980WR09137

II. CONTROLLING OFFICE NAME AND ADORESS

Naval Electronic Systems Command PME-106-1

Washington, D.C. 20360

12. REPORT DATE

December 1979

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103

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18. SUPPLEMENTARY NOTES

19. KEY WORDS (Continue on reverse aide If necessary and identify by block number)

Satellite Communications Analog to Digital Conversion

20. ABSTRACT (Continue on reverse side It necessary and

A prototype SATCOM Signal Ana performs spectral analysis on UHF communications satellites Analog to Digital Control and channels to baseband analog s sentations while operating at either twelve or eight bits o The digital data thus derived

identify by block number)

lyzer (SSA) has been designed which

transponder signals from the Navy's As an integral part of the SSA, th£

Conversion subsystem converts four ignals into equivalent digital repre-

variable sampling rates and offering f resolution of the analog signal.

is presented to an array processor

DD , ^NRM73 1473

EDITION OF 1 NOV 55 IS OBSOLETE

S/N 0102-014-6601 I

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for Fast Fourier Trnasform processing. This report documents the design and construction of the Analog to Digital Control ai| Conversion subsystem.

UNCLASSIFIED

n SECURITY CLASSIFICATION OF THIS P *GE(When Data Enter

ABSTRACT

A prototype SATCOM Signal Analyzer (SSA) has been de- signed which performs spectral analysis on transponder sig- nals from the Navy's UHF communications satellites. As an integral part of the SSA, the Analog to Digital Control and Conversion subsystem converts four channels of baseband analog signals into equivalent digital representations while operating at variable sampling rates and offering either twelve or eight bits of resolution of the analog sig- nal. The digital data thus derived is presented to an array processor for Fast Fourier Transform processing. This report documents the design and construction of the Analog to Digi- tal Control and Conversion subsystem.

TABLE OF CONTENTS

I. INTRODUCTION ------------------ 12

A. BACKGROUND ----------------- 12

B. PROTOTYPE SYSTEM GOALS ----------- 12

C. SCOPE OF THIS REPORT ------------ 13

D. THE PROTOTYPE SSA SYSTEM ---------- i3

E. ANALOG-TO-DIGITAL CONTROL AND CONVERSION SUBSYSTEM- ----------------- 15

II. DESIGN CONSIDERATIONS- ------------- 17

A. BASIC DESIGN CONSIDERATIONS- -------- 17

B. SINGLE VERSUS DUAL CHANNEL ANALOG-TO- DIGITAL CONVERSION ------------- 17

1. Sampling Requirements- --------- ig

2. Hardware Requirements- --------- 13

3. Image and Zero Frequency Considerations- 19

4. System Compatibility ---------- 19

C. EQUIPMENT SELECTION- ------------ 20

1. Sample Rate Requirements -------- 20

2. Bit Resolution Requirements- ------ 21

3. Equipment Selection- ---------- 21

III. DETAILED OPERATION --------------- 23

A. INTRODUCTION ---------------- 23

B. ADC BOARD- ----------------- 23

1. Introduction -------------- 23

a. Functions- ------------- 23

b. Inputs --------------- 26

c. Outputs- -------------- 26

d. Implementation ----------- 28

e. ADC Board Sections --------- 39

2. Synchronization Section- -------- 30

a. Introduction ------------ 30

b. Master Pulse ------------ 30

c. Sample -Command Pulse -------- 33

d. Start-Convert Pulse- -------- 33

e. HI/LOW-SELECT Signal Buffering and Inversion- ------------- 34

3. Sample-and-Hold Section- -------- 35

a. Introduction ------------ 35

b. LM-318 Operational Amplifier - - - - 35

c. Power and Overvoltage Protection - - 35

d. Sample-and-Hold Module, DATEL-SHM-

UH ----------------- 37

4. Analog-to-Digital Conversion Section - - 37

a. Introduction ------------ 37

b. Low Speed Analog-to-Digital Converter, DATEL ADC-EH12B3- - - - - 3 8

c. High Speed Analog-to-Digital Converter, TRW TDC-1001J ------ 42

5. Digital-Data-Selection Section ----- 45

a. Introduction ------------ 45

b. Output Formats ----------- 45

c. Data Latching- ----------- 47

d. Data Multiplexing- --------- 48

C. ADC CONTROL BOARD- ------------- 49

1. Introduction -------------- 49

a. Functions- ------------- 49

b. Inputs --------------- 49

c. Outputs- -------------- 49

d. Implementation ----------- 50

e. ADC Control Board Sections ----- 52

2. Pulse Forming/Power Protection Section - 52

a. Introduction ------------ 52

b. SAMPLE-ENABLE Signal -------- 52

c. Pulse Generation ---------- 55

d. Reference Signals- --------- 55

3. Divider Network- ------------ 55

a. Introduction ------------ 55

b. Sample-Frequency Generation- - - - - 55

4. Frequency-Selection Section- ------ 60

a. Introduction ------------ 60

b. Sample-Frequency Selection ----- gg

c. HI/LOW-SELECT Signal -------- 65

D. ADC TEST BOX ---------------- 55

1. Introduction -------------- 55

2. Inputs/Outputs ------------- 66

3. Implementation ------------- 66

4. Operation- --------------- 68

a. HI/LOW Test Mode ---------- 68

b. SAMPLE-FREQUENCY Test Mode ----- 70 IV. FUTURE DESIGN CONSIDERATIONS ---------- 73

V. CONCLUSION ------------------- 75

APPENDIX A - DUAL CHANNEL ANALOG-TO-DIGITAL

CONVERSION THEORY ------------ 76

APPENDIX B - SPECIFICATION TABLES- ---------- 7g

APPENDIX C - CALIBRATION PROCEDURES- --------- 33

APPENDIX D - PIN CONNECTIONS ------------- 86

APPENDIX E - COMPONENT LISTS ------------- 97

LIST OF REFEERENCES- - _-_-_-________ 1Q2

INITIAL DISTRIBUTION LIST- -------------- 103

LIST OF FIGURES

1. Block Diagram of the Prototype SATCOM Signal Analyzer- -------------------- 14

2. Block Diagram of the Analog-to-Digital Con- trol and Conversion Subsystem ---------- 24

3. Block Diagram of ADC Board Operation- ------ 27

4. ADC Board Component Layout- ----------- 29

5. Synchronization Section Circuit Diagram ----- 31

6. Synchronization Section Timing Diagram- ----- 32

7. Sample-and-Hold Section Circuit Diagram ----- 36

8. Analog-to-Digital Conversion Section

Circuit Diagram ----------------- 39

9. Low-Speed Analog-to-Digital Conversion

Timing Diagram- ----------------- 40

10. High-Speed Analog-to-Digital Conversion

Timing Diagram- ----------------- 44

11. Digital-Data-Selection Section Circuit Diagram- - 46

12. ADC Control Board Component Layout- ------- 51

13. Block Diagram of ADC Control Board Operation- - - 53

14. Power Protection/Pulse Forming Section

Circuit Diagram ----------------- 54

15. Divider Network Circuit Diagram --------- 57

16. Block Diagram of Sample-Frequency Generation- - - 58

17. Frequency-Selection Section Circuit Diagram - - - 62

18. ADC Test Box Circuit Diagram- ---------- 67

19. ADC Test Box- ------------------ 69

20. Switch Configurations -------------- 71

21. Block Diagram of Dual Channel

Analog-to-Digital Conversion- ---------- 77

LIST OF TABLES

I. Analog-to-Digital Control and Conversion

Subsystem Input/Output Specifications ----- 25

II. Offset Binary and Two's Complement Data

Formats -------------------- 41

III. Switch Settings for Tentative Sampling

Frequencies ------------------ 61

IV. Sample Frequency Selection- ---------- 64

V. DATEL SHM-UH Specifications ---------- 80

VI. DATEL ADC-EH12B3 Specifications -------- 81

VII. TRW TDC-1001J Specifications- --------- 82

VIII. ADC Control Board Pin Connections ------- 87

IX. ADC Board Pin Connections ----------- 93

X. ADC Control Board Components List ------- 93

XI. ADC Board Components List ----------- 99

XII. ADC Test Box Components List- --------- ioi

10

This page intentionally blank

11

I. INTRODUCTION

A . BACKGROUND

This project is one of a series of research projects con- cerning Navy UHF satellite communications {SATCOM) under- taken by the Satellite Communications Laboratory at the Naval Postgraduate School (NPS) . Previous research efforts include, but are not limited to, the preparation and evalua- tion of a shipboard Radio Frequency Interference (RFI) mea- surement package (Refs. 1-3), the design and construction of the development model SATCOM Signal Analyzer (Refs. 4-6), and the measurement of transponder oscillator drift of the GAPFILLER satellite (Ref. 7). The project which constitutes the basis of this report had its beginning in late 1978 when this laboratory was funded by PME 106-1 of the Naval Elec- tronic Systems Command (NAVELEX) to develop a prototype ver- sion SATCOM Signal Analyzer (SSA) system. Upon successful completion and field testing of the prototype, production models will replace the existing monitoring systems at various Naval Communications Stations (NAVCOMMSTA' s) and will be used to perform various measurements on Navy UHF communications satellite transponders while operating in orbit.

B. PROTOTYPE SYSTEM GOALS

The development of the prototype is based on the provision

12

of all equipment necessary to make real-time measurements at NAVCOMMSTA' s . This equipment must have the capability to: 1) perform high speed spectral analyses and frequency mea- surements in the UHF (240-320 MHz) band using digital techni- ques; 2) monitor authorized users of the Navy SATCOM system, including the GAPFILLER and FLTSATCOM series satellites; 3) perform selective monitoring when the NAVCOMMSTA is in the footprint of multiple satellites; 4) characterize RFI signals through the use of an X-Y modulation display; and 5) operate in either manual or automatic (computer control) modes .

C. SCOPE OF THIS REPORT

Figure 1 is a block diagram of the prototype SSA system. This report documents the design and construction of the Analog-to-Digital Control and Conversion subsystem.

D. THE PROTOTYPE SSA SYSTEM

The prototype SSA system has been designed around a PDP- 11/34 minicomputer. Standard peripherals have been pro- vided which made the system self sufficient and readily adaptable to existing NAVCOMMSTA power transceiver and an- tenna systems. Four identical and independent receiver paths have been incorporated to enable the system to continue operation in the event of component failures in any of these channels. High speed digital processing of signal data is accomplished through the use of an Analogic AP-400 array processor which operates under control of the PDP-11/34.

13

Quad 0E-82A

AN/WSC-5 Modified #1

u

AN/WSC-5 Modified #2

Test

RF UNIT #1

I

Single W^0E-82A

Antenna Control

Test

RF UNIT #2 Z3Z

Test

SIGNAL SELECTION UNIT

**

MM

Spectrum Receivers

Analog /Digita I ^* CntHs 8 Cnvertrs

Array « Processors

l I O

5

10MHz

_| PDP- 11/34 Minicomputer

I

Mass Memory

Printer

Control

Dual Graphics

I

AM/FM Receiver

U.

Frequency Receivers

Analog Interface

I

Counter

A/D

Analog

Tape

Recorder

Counter

X-Y

Modulation Di splay

Keyboard

-$> Unibus Interconnection «$>„ Inputs include sample frequency select.

All Frequencies II 1111

Frequency Multiplier

Test Unit

Synthesizer

Test

Power Amp

XMIT

Rubidium

Frequency

Standard

Figure 1 Block Diagram Of The Prototype SATCOM Signal Analyzer

14

The primary interface with the system operator is the dual graphics subsystem, consisting of two 17-inch , 60-Hz (non- interleaved) , raster scan displays. Each of these units has the capability to display a single spectrum or nine separate spectra arranged in a three by three matrix format. Provi- sions have been made for hard copy reproduction of the infor- mation being displayed.

E. ANALOG-TO- DIGITAL CONTROL AND CONVERSION SUBSYSTEM

As may be observed in Figure 1, the Analog-to-Digital Control and Conversion subsystem is the interface between the Spectrum Receivers and the Array Processor. Within each of the four signal paths in the Spectrum Receiver, an incoming analog signal is downconverted to baseband fre- quency and bandwidth limited to a bandwidth appropriate to the desired spectral resolution. The Analog-to-Digital Con- trol and Conversion subsystem converts this baseband signal into an equivalent digital "word" which in turn is presented to the AP-400 for array processor Fast Fourier Transform (FFT) processing.

In order to accomplish the above task, and to provide a high degree of flexibility in the spectral processing capa- bilities of the prototype SSA, design considerations required that the Analog-to-Digital Control and Conversion subsystem be capable of the following operations :

1. Sample-and-hold an analog signal at a maximum 2 MHz clock rate;

2. Analog-to-digital convert the sampled signal at a

15

maximum 2 MHz rate with eight bits of resolution, or a maxi- mum 500 kHz rate with twelve bits of resolution;

3. Select sampling frequency rates for analog-to-digital conversion (ADC) under control of the PDP-11/34;

4. Select sampling frequency rates for the X-Y modula- tion display under control of the PDP-11/34;

5. Provide an interrupt of the ADC process in the event of failure of any of the power supplies;

6. Generate appropriate "handshake" signals to the AP- 400 array processor; and

7. Be compatible in all respects with standard PDP-11/34 hardware and software.

Initial attempts to obtain an ADC system which would meet the above requirements revealed that no such units were commercially available. Accordingly, the Analog-to-Digital Control and Conversion subsystem was designed and constructed in this laboratory. The completed subsystem consists of five printed circuit (PC) boards: 1) four identical ADC boards (one per receiver signal path) which perform the actual ana- log-to-digital conversions; 2) one ADC Control Board which controls each of the ADC Boards and is in turn controlled by the Control Bus (also designed at NPS) which is driven by a DRIIC via the UNIBUS; and 3) an ADC Test Box to enable limi- ted testing of any of the ADC Boards.

16

II. DESIGN CONSIDERATIONS

A. BASIC DESIGN CONSIDERATION

The prototype SSA system as depicted in Figure 1 was de- signed to be completely contained (with the exception of 0E- 82A antenna and AN/WSC-S transceivers) within five standard 19 inch racks. This represents a dramatic space reduction when compared with the SATCOM Signal Analyzer (developmen- tal version) which performs the same functions (see refer- ences 4-6) as the prototype system but occupies 13 racks. Analogously, the Data Acquisition Unit of the SSA (develop- mental version) occupies one-half of a rack while the Ana- log-to-Digital Control and Conversion subsystem of the SSA prototype is wholly contained on five PC boards. Much of the reduction of space was obtained by performing the analog-to- digital conversions in the single vice dual channel mode.

B. SINGLE VERSUS DUAL CHANNEL ANALOG-TO-DIGITAL CONVERSION As described in Appendix A, dual channel analog-to-digi- tal conversion involves the simultaneous mixing (down-con- version) of an RF or IF signal with two equal magnitude, quadrature phase related local oscillator frequencies. The two down-converted signals are thus in phase quadrature with each other so that after analog-to-digital conversion, may be thought of as representing the "real" and "imaginary" components of a complex waveform. On the other hand, single

17

channel analog-to-digital conversion involves the mixing of an RF or IF signal with a single local oscillator frequency. Analog-to-digital conversion of this down converted signal results in a representation of the "real" component of a waveform. Each of these conversion schemes offers advantages to the system designer.

1. Sampling Requirements

Nyquist sampling theory states that an analog signal may be completely reconstructed from sampled values if the sampling rate is at least twice the highest frequency com- ponent contained within the signal. For spectral analysis this implies that each resolution unit (frequency line) re- quires two samples values. Dual channel conversion inherently provides these two values in the form of a "real" and "ima- ginary" component for each resolution unit, and sampling may thus be carried out at a rate equal to the highest frequency component within the analog signal. Therefore, for a given analog-to-digital converter, dual channel conversion offers the opportunity to either examine twice the bandwidth or operate at one-half the rate as in the single channel case. Inasmuch as the technology exists to adequately support the higher sampling rates required in single channel conversion, this limitation was considered acceptable in the design of the Analog-to-Digital Control and Conversion subsystem.

2 . Hardware Requirements

Dual channel analog-to-digital conversion requires two identical processing channels (sample-and-hold modules,

18

analog-to-digital converters, supporting circuitry) to simul- taneously convert the quadrature related analog signals into the "real" and "imaginary" components of a complex data point Single channel conversion requires only one processing chan- nel, thereby reducing the number of components by one-half. This was considered highly advantageous in light of the space limitations imposed on the SSA prototype design.

3 . Image and Zero Frequency Considerations Performing spectral analysis by the dual channel

technique results in a displayed spectrum which may contain misleading information. As explained in Appendix A, dual channel conversion results in a D.C. value in the baseband signal which represents the component of the RF signal at the local oscillator frequency. This appears in the spectral display as a signal at D.C. or zero frequency. Similarly, image frequencies may appear in the spectral display due to imbalances in the gains of the processing channels in the dual channel case. Either zero or image frequencies could lead the unsuspecting system operator to erroneously con- clude that the R.F. signal contained components that are not in fact present. The fact that neither of these phenomena are present in single channel conversion, coupled with the fact the production versions of the SSA may eventually be operated by unsophisticated operators, make the latter tech- nique both advantageous and desirable.

4 . System Compatibility

Both conversion techniques are easily adaptable to

19

digital processing. However, dual channel conversion re- quires double the amount of computer interface for adequate control and monitoring and may restrict the flexibility of the host computer. Additionally, the single channel con- version technique lends itself readily to audio monitoring (and recording) of the baseband signal. This capability does not exist in the dual channel case as a result of the pre- baseband division of the analog signal.

C. EQUIPMENT SELECTION

1. Sample Rate Requirements

The minimum acceptable sampling rate for the Analog- to-Digital Control and Conversion subsystem is the Nyquist rate (see Section II. B. 1.) . When this criterion is applied to a baseband signal, the sampling rate equals twice the band- width of that signal. However, if the bandwidth is taken, as is usually the case, as the half-power (or 3 dB) band- width, consideration must be given to aliasing. Aliasing results from the fact that a rectangular bandpass filter (BPF) is virtually impossible to implement and that a signal passed through such a BPF will have sloping, rather than abrupt, leading and trailing edges. If this signal is then sampled at the Nyquist rate, considerable distortion in the resultant spectrum may occur. The solution to aliasing is to sample at a rate based on a wider bandwidth, i.e., the 30 dB down bandwidth, where the effects of aliasing are not as significant. In the design of the Analog-to-Digital Control and Conversion subsystem, a rate of 2 MHz was considered

20

adequate to successfully sample the satellite's wideband trans- ponder channel while a rate below 500 kHz was deemed appro- priate for sampling the narrowband channels.

2 . Bit Resolution Requirements

The analog-to-digital conversion of any signal re- sults in the generation of quantization noise which is added onto the noise of the input signal. The quantization noise effect is 6 dB of SNR per bit of resolution. Determination of the number of bits used in the digital representation of the analog signal is thus a tradeoff between the desired dy- namic range of the analog-to-digital converter and tolerable levels of quantization noise. Experience gained in this laboratory while operating the developmental SATCOM Signal Analyzer (see references 4-6) indicated that eight bits of resolution were adequate for the wideband channel and were within the realm of existing technology. Similarly, 12 bits of resolution were considered adequate for the representation of signals in the narrowband channels.

3 . Equipment Selection

The major functional components of the Analog-to- Digital Control and Conversion subsystem are the sample -and- hold module and two analog-to-digital converters. For pur- poses of clarification, the remainder of this thesis will refer to the high-speed analog-to-digital converter as that converter which operates at a 2 MHz rate and provides eight bits of resolution; the low-speed analog-to-digital converter as the converter which operates at or below a 500 kHz rate

21

providing 12 bits of resolution. Selection of the components to be used to fulfill the design requirements involved com- parisons of existing hardware based on the following factors:

a. Specifications;

b. Cost;

c. Power supplied required;

d. Power dissipation; and,

e. Size

Based on the above criteria, the sample-and-hold module and low-speed analog-to-digital converter selected were the DATEL SHM-UH and DATEL ADC-EH12B3, respectively. In the case of the high-speed analog-to-digital converter, three units were selected for laboratory evaluation — the DATEL ABC-VH8B3, the TRW TDC-1001J, and the DDC (Digital Devices Corporation) ADC-1210. In each case the evaluation consisted of implementing the device, its supporting circui- try and power supplies on SK-10 breadboards and then applying signals similar to those which would be encountered in the operating system. Upon completion of the evaluations the TRW TDC-1001J was selected as the high-speed analog-to-digi- tal converter.

22

III. DETAILED OPERATION

A. INTRODUCTION

The Analog-to-Digital Control and Conversion subsystem receives a baseband analog signal from each of the four chan- nels of the Spectrum Receiver. Within the subsystem these four analog signals are independently analog-to-digital con- verted at various sampling rates determined by the system operator. The resultant digital representations of the ana- log inputs are then presented to a bank of four array pro- cessors for Fast Fourier Transform processing (see Figure 2) . The subsystem consists of four identical printed circuit (PC) boards (ADC Boards) containing the analog-to-digital conver- sion circuitry and one PC board (ADC Control Board) contain- ing the requisite circuitry to control the four ADC Boards and the X-Y display analog-to-digital converter. The system operator may perform limited testing on any of the ADC Boards through the use of the ADC Test Box in conjunction with the ADC Control Board. Table I provides the required external inputs and outputs of this subsystem.

B. ADC BOARD

1. Introduction a. Functions

Each of the four ADC Boards perform the following functions: 1) sample-and-hold an incoming signal at a maximum

23

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24

TABLE I

ANALOG TO DIGITAL CONTROL AND CONVERSION SUBSYSTEM INPUT/OUTPUT SPECIFICATIONS

Power Supplies:

Analog Inputs: Number

Voltage Range

Maximum input Voltage Reference Input: Sampling Rates:

High Speed

Low Speed Range

Selection Control Digital Outputs:

Format

Low Speed High Speed

Handshake

Clock Outputs for X-Y ADC Reference

Sample Frequency Range Selection Control

+5 volts, + 15 volts (provided by chassis connections)

4 (1 per Spectrum Receiver channel)

+ 10 volts

+ 15 volts

2 0 MHz @ 13 dBm (sine wave)

2 MHz

781 Hz - 500 kHz (selectable)

3 bits per analog input

Two's complement or offset binary (selectable)

One 12 bit word

Two 8 bit words (successive sample values) in parallel

150 nanosecond positive pulse (AP-400 compatible)

20 MHz square wave 781 Hz - 96.2 kHz 2 bits

25

2 MHz clock rate; 2) analog-to-digital convert the sampled signal at one of five sampling rates; 3) output digital data in a format compatible with the AP-400 (array processor) ; and, 4) generate "handshake" signals to the AP-400. As previously mentioned, each of the ADC Boards operates in conjunction with one channel of the Spectrum Receiver subsystem. Inasmuch as the ADC Boards are identical, future reference in this thesis to "the" board may be taken to mean any one of the ADC Boards. A generalized block diagram of the operation of the ADC Board is provided as Figure 3.

b. Inputs

The ADC Board receives all operating and control signals from the ADC Control Board. These signals are as follows :

(1) Sample-Frequency Clock;

(2) HI/LOW-SELECT Signal;

(3) SAMPLE-ENABLE Signal; and,

(4) 20 MHz reference Clock

These signals and their functions will be explained in detail later in this thesis. The ADC Board also receives the base- band analog signal from the corresponding channel of the Spectrum Receiver.

c . Outputs

The ADC Board generates a 12 bit digital represen- tation of the input analog signal while operating in the low-speed mode and an eight bit representation in the high- speed mode. The appropriate digital signals to the mode of

26

. HI/LOW-SELECT

SAMPLE- FREQUEN

CLOCK

5»

SYNCHRONIZATION SECTION

HI/LOW-SELECT

. START-CONVERT

ANALOG DATA

■>

SAMPLE-ENABLE

^

SAMPLE COMMAND

\1/

SAMPLE AND HOLD SECTION

SAMPLED ANALOG DATA

A1Z

ANALOG-TO-DIGITAL CONVERSION SECTION

<r

<■

ONE 12 (OR TWO 8) BIT WORDS AND LATCHING SIGNALS

XL

DIGITAL DATA SELECTION SECTION

<■

^

1. HANDSHAKE

2. 12 or 16 BITS OF DATA

TO AP-400

ar!ra

Y PROCESSOR

Figure 3 ADC BOARD OPERATION

27

operation and the "handshake" signal are routed to the AP-400 array processor. Additional outputs include a +5 volt signal which is provided to the ADC Test Box and a common GROUND signal provided to the ADC Control Board, d. Implementation

The ADC Board is wholly contained on a standard PDP-11 QUAD size printed circuit (see Figure 4) . Design lay- out and basic board construction were accomplished through the use of the facilities of the Etching Laboratory at NPS. The ADC Boards are designed to be mounted vertically on, and draw all power (+5 volts, +5 volts, GROUND) from, a standard PDP-11 backplane contained within a PLESSEY PM-1150/5 power chassis. Inputs from the ADC Control Board are brought onto the board via a CANNON DAM-7W25A Connector assembly which has provisions for two coaxial fittings and five standard pin connections. The signals carried by coaxial cable (20 MHz reference clock and Sample Frequency clock) are routed to their destinations via cable on the component side of the board. The analog signal interfaces with the ADC Board through a standard SMA Bulkhead fitting. Outputs from the ADC Board to the AP-4 00 exit the board via an ANSLEY 609- 615M 34 pin ribbon cable mating connector. The GROUND and +5 volt outputs (to the ADC Control Board and ADC Test Box, respectively) are routed via the CANNON 7W2 5A connector. Pin connections for all connectors and backplane slots may be found in Appendix D.

28

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29

e. ADC Board Sections

The ADC Board has been subdivided into five func- tional sections. This division not only simplifies discussion of board operation but also represents an orderly progression in the signal processing which occurs on the board. The four sections are the Synchronization section, the Sample-and-Hold section, the Analog- to-Digital Conversion section and the Digital-Data-Selection section. An in-depth discussion of ADC Board operation will be accomplished by considering the operations performed within each section. The reader is ad- vised to familiarize himself with Figure 3 prior to the reading of the following sections. 2 . Synchronization Section

a. Introduction

The Syncrhonization section performs the following functions: 1) generation of the Sample-Command signal; 2) generation of the Start-Convert signals for both analog- to-digital converters; 3) buffering and inversion of the HI/ LOW-SELECT signal; and, 4) selective enabling of the low-speed Start-Convert signal. The schematic diagram for this section is given in Figure 5, while Figure 6 depicts the time rela- tionship among the various pulses generated in this section.

b. Master Pulse

The 40 nanosecond positive-going Master Pulse (MP) and its complement (MP) are generated by Ul, a 74121 mono- stable multivibrator. Triggering information is provided by the trailing edge of the Frequency clock which arrives

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directly at pins 3 and 4 via the center conductor of a coaxial cable. The braid of the cable is grounded adjacent to the integrated circuit and a 50 ohm impedance matching resistor is placed across the braid and center conductor. The width of the Master Pulse is determined by the internal resistor/25 picofarad capacitor combination and was selected to meet the 35 nanosecond ( + 10 nanosecond) requirement of the sample-and- hold module with tolerance for variations in capacitor and resistor values.

c. Sample-Command Pulse

The sample-and-hold module (DATEL SHM-UH) re- quires a Sample- Command signal of the previously mentioned width which is capable of sourcing 100 milliamperes of cur- rent. Accordingly, the complement of the Master Pulse (MP) is simultaneously provided to pins 1 and 13 of U3, a 74S140 dual 50 ohm line driver. All other inputs to U3 are held high so that the negative going pulse (MP) results in a positive pulse at the outputs. These outputs are combined, and, in conjunction with a 100 ohm pull up resistor, provide the Sample- Command pulse which is of correct width and current sourcing capability to drive the sample-and-hold module.

d. Start-Convert Pulse

A 200 nanosecond positive going pulse is used as the Start-Convert pulse for both analog-to-digital converters. This width was selected to exceed the minimum requirements (high speed converter — 50 nanoseconds, low speed--100 nano- seconds) and to provide adequate tolerance for resistor/

33

capacitor values. The pulse is generated by U2, a 74121 mono- stable multivibrator with the width controlled by a 3.3 kilohm/ 82 picofarad combination across pins 10 , 11 and 14. Trigger- ing is supplied by the trailing edge of the Master Pulse, applied to pins 3 and 4. Use of this pulse for triggering provides approximately 85 nanoseconds of delay from the be- ginning of the sampling evolution until the analog-to-digital conversions begin, thus assuring that the acquisition time of the sample-and-hold (50 nanoseconds) has elapsed.

e. HI/LOW-SELECT Signal Buffering and Inversion

The HI/LOW-SELECT signal and its complement are the most widely used control signals in the analog-to-digital conversion process. Because of the number of loads it drives on the ADC Board, it is buffered by double inversion at U4 , a

HEX Inverter. The complement (HI/LOW-SELECT) is generated by a single stage of inversion. In the Synchronization sec- tion, the HI/LOW-SELECT signal is used to enable the low- speed Start-Convert signal. This enabling is required due to the low-speed analog-to-digital converter having a maxi- mum conversion rate to 500 kHz. The use of a common Start- Convert signal to both converters implies that in the high- speed mode (conversion rate = 2MHz) , the low-speed converter would be driven at four times its maximum rate. To avoid this situation, the low-speed Start-Convert pulse-train is logically OR-ed with the HI/LOW-SELECT signal (at U5) , pro- ducing a constant "high" output and thereby disabling the low- speed converter .

34

3 . Sample-and-Hold Section

a. Introduction

In the Sample-and-Hold section the analog signal from the associated channel of the Spectrum Receiver is sam- pled at the desired sample rate. The section is designed around the DATEL SHM-UH sample-and-hold module and associated protection circuitry. The schematic diagram for this sec- tion is given in Figure 7.

b. LM-318 Operational Amplifier

As shown in Figure 6, the baseband analog signal is applied to a unity gain LM-318 Operational Amplifier (OP-AMP) designed to operate in the differential mode. This configuration reduces ground loop noise. Laboratory experi- mentation revealed that operation in this mode with + 15 volt power supplied results in a saturation voltage of + 14 volts, which exceeds the input overvoltage protection range of the SHM-UH. The solution to this potential problem will be dis- cussed in the following section.

c. Power and Overvoltage Protection

Experience in the operation of the SHM-UH in this laboratory has demonstrated that it is susceptible to failure if an analog signal is applied to the module without all power supplies operating. In order to avoid this occurrence, a CLARE PRMA1A05C reed relay was placed between the LM-318 OP- AMP and the analog input of the SHM-UH. The controlling voltage for this relay is the SAMPLE-ENABLE signal which is generated on the ADC Control Board. As previously mentioned,

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the input overvoltage protection range of the SHM-UH (+ 10 volts) is less than the saturation voltage of the LM-318 OP-AMP. In order to protect against over-voltage inputs, a two-to-one divider network has been implemented immediately prior to the reed relay which ensures that the maximum in- put voltage to the SHM-UH is approximately + 7 volts.

d. Sample-and-Hold Module, DATEL SHM-UH

The analog baseband signal from the Spectrum Receiver is sampled by the DATEL SHM-UH sample-and-hold module. It is controlled by the 40 nanosecond Sample-Com- mand input generated in the Synchronization section and has a + 5 volt full scale input range. The device is capable of operation at a sampling rate of 10 MHz which is well in ex- cess of the maximum rate employed in this system. The out- put sampled values are noninverted + 5 volt levels which are directly compatible with the input of the low-speed analog- to-digital converter and require reduction and offset to ensure compatibility with the high-speed converter input range. The SHM-UH has an internal offset trimpot which is adjusted according to the instructions contained in Appendix C. Detailed specifications of the SHM-UH may be found in Appendix B.

4 . Analog-to-Digital Conversion Section

a. Introduction

The Analog-to-Digital Conversion section performs two functions: 1) analog-to-digital conversion of the sam- pled analog data with eight or twelve bits of resolution; 2) generation or conditioning of End-of-Convert (EOC) signals

37

to ultimately be used as latch commands. The section was designed around the DATEL ADC-EH12B3 and TRW TDC-1001J ana- log-to-digital converters and all supporting circuitry. Figure 8 is a schematic diagram for this section.

b. Low-Speed Analog-to-Digital Converter, DATEL ADC-EH12B3

Sampled analog signal values from the SHM-UH are routed directly to the DATEL ADC-EH12B3. This device provides a 12 bit representation of the input signal value and is capable of operation at a maximum rate of 500 kHz. It is controlled by the 200 nanosecond Start-Convert pulse generated in the Synchronization section. As demonstrated in Figure 9, the parallel output data and EOC signal are available approximately 2 microseconds after the leading edge of the Start-Convert pulse. The twelve bits of paral- lel output data is available in offset binary or two's com- plement format. The preferred option is selected through the use of a jumper wire on the reverse side of the ADC Board Connecting the cable between pads J and A provides the offset binary format while connecting the wire between pads J and B provides the two's complement format (see Table II). The EOC signal is a negative-going pulse which occurs 100 nanoseconds after the conversion is complete. This signal is then triple inverted by the inverters in U20 and provided to the Digital- Data-Selection section for use as a latching signal. Instruc- tions for the adjustment of the external 20 ohm trimpot (GAIN ADJUST) and 2 00 ohm trimpot (OFFSET ADJUST) are located in Appendix C, while Appendix B provides detailed operating

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TABLE II OFFSET BINARY AND TWO'S COMPLEMENT DATA FORMATS

LOW- SPEED CONVERSION FORMATS

Offset Binary Two's Complement Analog Input Voltage ( J-A Connection) * (J-B Connection) *

+5.	,00	volts	1111	1111	1111	0111	1111	1111
+ 2.	,50	volts	1100	0000	0000	0100	0000	0000
0.	.00	volts	1000	0000	0000	0000	0000	0000
-2,	,50	volts	0100	0000	0000	1100	0000	0000
-5.	.00	volts	0000	0000	0000	1000	0000	0000

*Pads A, B and J are located adjacent to pin 1 of the ADC-EH12B3 module.

HIGH-SPEED CONVERSION FORMATS

Offset Binary Two's Complement Analog Input Voltage (J-A Connection) * (J-B Connection) *

0.000 volts	1111	1111	0111	1111
-.125 volts	1100	0000	0100	0000
-.250 volts	1000	0000	0000	0000
-.375 volts	0100	0000	1100	0000
-.500 volts	0000	0000	1000	0000

*Pads A, B and J are located adjacent to pin 1 of U22.

41

specifications of the ADC-EH12B3.

c. High-Speed Analog-to-Digital Converter, TRW TDC-1001J

The TRW TDO100U analog-to-digital converter provides an eight bit representation of the analog input value and is capable of operation at a maximum rate of 2.5 MHz. The input analog voltage range is + .25 volts around a center value of -.25 volts , which requires an offset and range adjustment of the sampled values originating at the SHM-UH sample-and-hold module. The range adjustment was accomplished by a twenty-to-one voltage division of the analog signal and offset adjustment was similarly accomplished by ten-to-one voltage division of the -5 volt power supply. Instructions for the requisite adjustment of the 50 kilohm trimpot to ob- tain the offset value are found in Appendix C. Laboratory experimentation revealed that this module is highly suscep- tibel to instabilities in the + 5 volt power supplies. Inas- much as -5 volts is not available on the PDP-11 backplane, and to provide essentially ripple free supply voltages, it was decided to provide these supplies by + 5 volt regulators. The reference input (-5 volts) applied to pin 13 is obtained by a ten-to-one division of the -5 volt regulator output through the use of a fixed 1 kilohm resistor and a 50 kilohm trimpot. Appendix C contains instructions for this adjustment The 20 MHz reference clock required by this module is applied directly to pin 18 via the center conductor of a coaxial cable which is terminated across a 50 ohm impedance matching re- sistor. The output of the TDC-1001J is eight bits of parallel

42

data presented in inverted offset binary format, i.e., the more negative full scale value (-.5 volts) appears as eight logical "ones". Converting this output to a true offset binary format is accomplished through the use of inverters in U20 and U22 . The output of these inverters may be converted into two's complement or offset binary format by making the same pad/ jumper cable connections as in the low-speed case (see Table II) . The EOC signal is used to control the output latch register internal to the device and thus occurs appro- ximately 110 nanoseconds prior to the output data being avail- able at pins 3-9 and 11 (see Figure 10) . The disparity in time, and the unique output format from the ADC Board to the AP-400 while operating in the high-speed mode, make this EOC signal unsuitable for use in the Digital-Data-Selection section which requires two separate latching signals during high-speed operation (see Section III, B.5.). Accordingly, the TDC-1001J EOC signal is applied as the triggering signal to U19, a 74121 monostable multivibrator, generating a 150 nanosecond positive-going pulse. This pulse is in turn ap- plied as the clock signal to a negative edge triggered J-K flip-flop (contained in U19) which is configured in the toggle mode. The use of the trailing edge of the pulse gen- erated in U19 as the clock signal to U18 ensures that the positive transitions occurring at either the Q or Q outputs are sufficiently delayed to act as latching commands. The flip-flop is enabled by the HI/LOW-SELECT signal and thus is disabled during operation in other than the high-speed mode.

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The Q output of the J-K flip-flop makes a positive transition upon the completion of the first conversion after the high- speed mode is selected (and all subsequent odd numbered con- versions) and hence is referred to as HIGH-SPEED-WORD-ONE-EOC. Similarly the Q output makes a positive transition upon com- pletion of the second conversion (and all subsequent even numbered conversions) and is referred to as HIGH-SPEED-WORD- TWO-EOC .

5 . Digital-Data-Selection Section

a. Introduction

The Digital-Data-Selection section performs three functions: 1) multiplexing of digital data and latching commands to the output latches; 2) latching the output data; and, 3) generation of the "handshake" signal to the AP-400. The schematic of this section is shown in Figure 11.

b. Output Formats

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bit "word" and all eight inputs of the eight bit "word", and the array processor is programmed to read these 24 bits as one "word" but to interpret them as two separate sample values. This technique allows the analog-to-digital conver- sions to be performed at a 2 MHz rate with the digital outputs being processed at a 1 MHz rate with no inherent loss of data The required "handshake" signal to the array processor (IP/TRS INTERRUPT) is a 150 nanosecond positive-going pulse indicating that data is ready at the processor inputs. This signal is generated by U21, a 74121 monostable multivibrator, with a 2.7 kilohn resistor/68 picofarad capacitor combination across pins 10, 11 and 14. During low-speed operation, triggering

is provided by the ADC-EH12B3 EOC signal while in the high- speed mode the trigger is provided by the HIGH-SPEED-WORD- TWO-EOC.

c. Data Latching

As demonstrated in Figure 11, output data from the Digital-Data-Selection section is made available to the AP-400 at various combinations of five 7417 5 quad memory latches (U8-U12) . In the low-speed mode of operation, the 12 output bits appear at the outputs of U10-U12, with latching commands

supplied by the positive transition of the ADC-EH12B3 EOC signal. The unused output latches (U8, U9) are disabled by the application of the HI/LOW-SELECT signal to pin one of both IC's. During high-speed operation, the eight digital data bits of the first conversion are applied to two inter- mediate latches (U13 , U14) with latching commands to these

47

latches by the HIGH-SPEED-WORD-ONE EOC signal. Upon comple- tion of the second high-speed conversion, these eight bits and the eight bits from the second conversion are latched directly into U8, U9 , Ull and U12, respectively, with latch- ing commands supplied by the HIGH-SPEED-WORD-TWO-EOC signal. In the high-speed mode of operation the unused output latch

(U10) is disabled by the HI/LOW-SELECT signal applied to pin one of that latch. Therefore, during high-speed operation the eight output bits of the first conversion are double lat- ched and all 16 bits are applied to the output latches simul- taneously. In both high-speed and low-speed modes the "hand- shake" signal appears at the output approximately 40 nano- seconds after the digital data appears at the outpus of the appropriate latches. This delay is attributable to the pro- pagation time of the monostable multivibrator (U21) generating this signal.

d. Data Multiplexing

In order to minimize the number of components utilized, the first eight data bits of the low speed mode and the eight bits from the second conversion in the high-speed mode utilize the same output latches (Ull, U12) . These 16 bits of data are multiplexed prior to the output latches by two 74157, quad two-to-one multiplexers (U16, U17) , with selection commands provided by the HI/LOW-SELECT signal. The latching commands to the five output latches (ADC-EH12B3 EOC and HIGH-SPEED-WORD-TWO-EOC) are similarly multiplexed through an additional 74157 (U15) which also has selection commands supplied by the HI/LOW-SELECT signal.

48

C. ADC CONTROL BOARD 1. Introduction

a. Functions

The ADC Control Board is designed to provide all control signals to each of the four ADC Boards. Accordingly, it performs the following functions: 1) conversion of a 20 MHz sinusoid into a 20 MHz pulse-train; 2) generation of all five Sample-Frequency-Clock signals; 3) generation of the SAMPLE-ENABLE signal; and, 4) generation of the HI/LOW-SELECT signal.

b. Inputs

The Master Control Bus of the PDP-11/34 provides all operating signals to the ADC Control Board. These sig- nals include three ADC Sample-Frequency-Selection signals for each of the ADC Boards and two Sample-Frequency-Selection signals for the X-Y modulation display. All operating fre- quencies in the SSA Prototype system are based on a 5 MHz rubidium standard. The 20 MHz sinusoidal input to the ADC Control Board is generated by the up conversion of the 5 MHz sinusoid in the frequency multiplication unit (see Figure 1) . Additionally, the ADC Control Board shares a common GROUND with each of the ADC Boards, the analog-to-digital converter of the X-Y Modulation Display, the Master Control Bus, and, when appropriate, the ADC Test Box.

c . Outputs

The ADC Control Board outputs the following sig- nals to each of the ADC Boards:

49

(1) 20 MHz reference clock;

(2) Sample frequency clock;

(3) SAMPLE ENABLE signal;

(4) HI/LOW SELECT signal.

Additionally, both of the clock signals are provided to the analog-to-digital converter of the X-Y Modulation Display, d. Implementation

The ADC Control Board was designed for implemen- tation on a standard PDP-11 QUAD size printed circuit board with a two inch extension in the direction of slot B (see Figure 12) . Use was made of the facilities of the NPS Etching Lab in the design layout and basic construction of the ADC Control Board. Inputs from the Master Control Bus arrive at this board via a ANSLEY 609-615M 16-pin ribbon cable mating connector which is equipped with a polarizing key to avoid incorrect mounting. The 20 MHz sinusoid is applied via coax- ial cable to a standard SMA Bulkhead fitting. Outputs to each of the four ADC Boards are routed via four CANNON 7W25A con- nectors which, as mentioned previously, have provisions for two coaxial fittings and five standard pin connections . The two clock signals for the X-Y Modulation Display exit the board via the outer two (of three) coaxial fittings on a CANNON 3W3S connector. The ADC Control Board will be mounted adjacent to the four ADC Boards within the PLESSEY power chas- sis and will draw all power supplies (+5 volts, +15 volts, GROUND) from appropriate connections on the PDP-11 backplane. Appendix D provides a listing of pin connections for all

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connectors and backplane slots.

e. ADC Control Board Section

As in the case of the ADC Boards, the ADC Control Board has been divided into functional sections to facilitate discussion of board operations. The operations performed within each of these areas will be presented in the following sections of this thesis. The three sections are the Pulse Forming/Power Protection section, the Divider Network, and the Frequency-Selection section. Figure 13 is provided as a generalized block diagram of the operation of the ADC Con- trol Board.

2 . Pulse Forming/Power Protection Section

a. Introduction

The Pulse Forming/Power Protection section performs three functions: 1) conversion of the 20 MHz sinusoid into a 20 MHz pulse-train; 2) generation of all reference frequen- cies for use in the divider network; and, 3) generation of the SAMPLE-ENABLE signal. The schematics of this section are presented in Figure 14.

b. SAMPLE-ENABLE Signal

As mentioned in Section III. A. 3., the application of an analog signal to the SHM-UH sample-and-hold module with one or more power supplies not operating is a failure condi- tion for this device. Accordingly, each of the three power supplies required for SHM-UH operation is provided to the input of a CLARE PRMA 1A05C to pull in the relay of that de- vice. An internal protection diode in each reed relay requires

52

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REFERENCE FREQUENCIES

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Figure 13 ADC CONTROL BOARD OPERATION

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that the more positive signal be applied to pin 2 and that the +15 volt inputs be routed through current limiting resistors (1 kilohm) . A +5 volt signal is then passed in series through the three relays and is routed to the ADC Boards as the SAM- PLE-ENABLE signal. Should one of the power supplied malfunc- tion, the corresponding relay would open causing the SAMPLE- ENABLE signal to go "OFF" and open the relay which passes the analog signal to the SHM-UH. Three Light-Emitting-Diodes (LED's) are mounted at the upper edge of the ADC Control Board for quick visual reference to power supply status. The normal, power-on, condition is indicated by an illuminated LED. c. Pulse Generation

The 20 MHz sinusoid from the frequency multiplica- tion unit is converted to a 20 MHz pulse train by application to the base of a 2N3945 high power NPN transistor configured as shown in Figure 14. Double inversion of the collector out- put at Ul provides TTL compatible levels as well as a 50% duty cycle. The collector and base resistor values were determined to provide flexibility in the transistor types which could be employed in this circuit. Laboratory testing of three dif- ferent transistors (2N3501, 2N3118, 2N3945) yielded satisfac- tory formation of the pulse train. The input sinusoid is de- signed to have a +13 dBm level; the circuit as designed works satisfactorily with sinusoidal input levels as low as +6 dBm, indicating that a 75% decrease in input level is tolerable. The 20 MHz pulse train is routed to the ADC Boards and X-Y Modulation Display where it serves as the reference clock for

55

the high-speed analog-to-digital converters, d. Reference Signals

The ADC Control Board is capable of producing one high-speed and four low-speed Sample-Frequency clock signals. The range of frequencies available provides a great deal of flexibility in resolution capability in the spectral analyses to be performed. Accordingly, this section of the board pro- vides three reference signals (10 MHz, 2 MHz, 200 kHz) to the Divider Network where the low-speed sampling frequencies are generated (Note: 2 MHz is also the high-speed sampling fre- quency) . As demonstrated in Figure 14, the 20 MHz pulse train is applied to U2, a D flip-flop designed to divide by two. This 10 MHz output signal is then routed to U3 , a 74161 con- figured to divide by five. Finally, the resultant 2 MHz signal is divided by ten at U5 , another 74161. These three reference frequencies are then routed to the Divider Network. 3 . Divider Network

a. Introduction

As previously mentioned, the Divider Network generates the low-speed sampling frequencies to be used in the spectral analyses by performing various divisions on the three reference frequencies. Figure 15 is a schematic of this section while Figure 16 provides a block diagram of the sam- ple frequency generation process.

b. Sample Frequency Generation

Each of the reference frequencies generated in the Pulse Forming/Power Protection section is routed to a

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variable modulo (up to 256) divider combination consisting of a 7420 dual input NAND gate, two 74161 divide-by-16 counters and two board-mounted, quad DPDT switches. This combination of components offers a great deal of flexibility in the sel- ection of sampling frequencies (by making available all prime number in the 0-256 range) and simplifies the implementation of predetermined sampling frequencies. The 10 MHz reference frequencies may be converted into sampling frequencies in the 39.1 kHz to 10 MHz range through the application of such a com- bination. Similarly, the 2 MHz reference frequency could be converted into sampling frequencies in the 7.8 kHz to 2 MHz range; the 200 kHz reference input into sampling frequencies in the 7 81 to 200 kHz range. Control of the exact sampling frequency desired is accomplished by manipulation of the two quad switch packages which in turn control the preset load inputs to the divider I.C.'s. Implementation of a particular sampling frequency is accomplished by first determining which of the above ranges is appropriate to the desired frequency. The divider modulo number is then determined by division of the corresponding reference frequency by the desired sampling frequency (round-off may be required) . The programming of the eight DPDT switches within each combination is determined by subtracting the modulo division number from 255 and convert- ing the result to a base two representation. The eight switches in each combination represent ascending powers of the base two (2,2 . . .) , reading from left to right. The UP position on each switch places a logical "1" on that switch's

59

output while the DOWN position places a logical "0" on the output. Using this technique, the binary representation of the result of the (255-modulo division number) subtraction is placed on the eight switches and the desired frequency is generated at pin nine of the right most 74161 in the com- bination. As demonstrated in Figure 15, the tentative values of the five sampling frequencies are 1.5 kHz, 12.0 kHz, 96.2 kHz, 333.3 kHz and 2.0 MHz (all values rounded to nearest tenth) and are designated sample frequencies 1-5 respectively. Table III lists the switch settings utitlized to obtain the low speed sampling frequencies. The sample frequencies thus generated are routed to the Frequency Selection section. 4. Frequency-Selection Section

a. Introduction

The Frequency-Selection section performs three functions: 1) selection of the desired sampling frequency for each ADC Board and the X-Y Modulation Display; 2) selec- tive disabling of each ADC Board and X-Y Modulation Display; 3) generation of HIGH/LOW-SELECT signal. The schematic repre- sentation of this section is provided as Figure 17.

b. Sample-Frequency Selection

The selection of the sample frequency for each ADC Board and the X-Y Modulation Display is accomplished through the use of five 74151 eight-to-one multiplexers (U-ll through U15) . The five sampling frequencies generated in the Divider Network are applied to the multiplexer for each of the ADC Boards (Ull - U14) while the multiplexer for the X-Y

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Modulation Display receives only Sample Frequencies 1-3. Design of this section includes the provision for the selec- tive disabling of any of the ADC Boards and/or the X-Y Modula- tion Display. The disabling signal is a logical "0" placed on the Sample-Frequency coaxial cable to the board being disabled. This signal is obtained by the application of a logical "1" ( + 5 volts )to the DO input of each multiplexer (pin 4), and is designated Sample Frequency 0. This value is in- verted by the corresponding 74S140 dual 50 ohm line device thereby creating the disabling signal. Selection of the desired sampling frequency is controlled by the Sample-Fre- quency-Selection signals received from the Master Control Bus of the PDP-11/34. The multiplexer controlling the output frequency to each of the ADC Boards receives a three bit selection signal which allows for the selection of all six sample frequencies. Inasmuch as the multiplexer for the X-Y Modulation Display has only four possible sample frequency options, it receives a two bit selection signal. Table IV correlates the Sample-Frequency-Selection signals to the re- sultant output signals. As previously mentioned, each output sample frequency, as well as the 2 0 MHz reference clock, is applied to a 74S140 component to provide sufficient current sourcing for transmission via coaxial cable. All output signals to ADC Boards one through four exit the ADC Control Board via connectors J-l through J-4 , respectively. Connec- tor J-5 is the interface for the two clock signals routed to the X-Y Modulation Display.

63

TABLE IV SAMPLE FREQUENCY SELECTION

Sample Frequency Select

Signal (to each 74151) Sample Frequency Sample Frequency

Pin 9 Pin 10 Pin 11 Number Value

0 0 0 0 None, wired to

+5 volts

0 0 1 1 1.5 kHz

0 10 2 12.0 kHz

0 1 1 3 9 6.0 kHz

10 0 4* 333.3 kHz

10 1 5* 2.0 MHz

* -- not available to multiplexer for X-Y Modulation Display (U15)

64

c. HI/LOW-SELECT Signal

The HI/LOW SELECT signal is used to control certain evolutions on the ADC Boards which are particular to the high- speed or low-speed modes of operation. In order to avoid con- fusion, the signal was designed to be at "high" level during high-speed operation (sample frequency 5 selected) and at a "low" level during low-speed operation (sample frequencies 0-4 selected) . As demonstrated in Table IV, the Sample-Frequency- Select signal from the Master Control Bus is the binary repre- sentation of the decimal number of the sample frequency being selected. The HI/LOW-SELECT signal is generated by the logical AND-ing of the most significant and least significant bits of the Sample-Frequency-Select signal for each ADC Board. This signal is not provided to the X-Y Modulation Display analog- to-digital converter since that device will always operate in one of the low-speed modes.

D. ADC TEST BOX

1. Introduction

The ADC Test Box was designed to enable the SSA operators to monitor the operation of any one of the ADC Boards under limited test conditions, and may, therefore, serve as either a learning tool or a maintenance trouble shooting device. Operation of the ADC Test Box is premised on the proper functioning of the ADC Control Board which supplies the majority of the inputs to the device. The test box is inserted into a functioning system between the ADC Control Board and the ADC Board and, through proper switch

65

selection, may remain completely passive and thereby allow (NORMAL) computer-controlled data exchange between the two boards. In the TEST modes, the ADC Test Box allows the following options: 2) selection of the sampling frequency; and, 2) selection of the mode of operation (low or high speed) Figure 18 presents the schematics of the implementation of these options.

2 . Inputs/Outputs

When the ADC Test Box is inserted between the ADC Control Board and the ADC Board, it remains transparent to the latter. This transparency is attributable to the signals arriving at the ADC Board in the same form whether the ADC Test Box is in the NORMAL mode or one of the TEST modes. Accordingly, the inputs to, and outputs from, the ADC Test Box are identical to the outputs of the ADC Control Board. These signals include the following:

a. Sample-Frequency clock;

b. HI/LOW-SELECT signal;

c. SAMPLE-ENABLE signal; and,

d. 20 MHz reference clock.

The inputs which are not included in the test options (20 MHz reference clock and SAMPLE-ENABLE signal) are simply routed through the ADC Test Box. The device receives +5 volts from the ADC Board and shares a common GROUND with both boards

3 . Implementation

The components comprising the ADC Test Box are socket mounted on a 3 inch by 3 inch printed circuit board which was

66

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designed and initially constructed at the NPS Etching Labor- atory. This PC board is mounted within a BUD ALU-108 3 alumi- num utility cabinet. Inputs from the ADC Control Board arrive at the ADC Test Box via the same bunched cable assembly that would normally be routed to the appropriate ADC Board and are similarly terminated in a CANNON DAM-7W25A connector. Outputs exit the test device via a bunched cable assembly (no connec- tor) which terminates in the CANNON DAM-7W2 5A connector on the ADC Board. The output cable assembly differs from the in- put assembly by the presence of an additional line on the for- mer which carries the +5 volt supply to the ADC Test Box from the ADC Board. The switches controlling the NORMAL or TEST modes of operation are mounted on the top of the box with functional labeling located adjacent to each switch (see Figure 19) .

4 . Operation

a. HI/LOW Test Mode

The HI/LOW test mode allows the operator to inter- rupt the computer controlled signal on the HI/LOW-SELECT sig- nal line and to manually control the high-speed or low-speed mode of operation on the ADC Board. The test mode is selected by positioning the HI/LOW toggle switch to the TEST-HIGH or TEST-LOW detents. In the TEST-HIGH position, a logical "1" is placed on the HI/LOW-SELECT signal line and the ADC Board is configured for high speed operation (testing) . Selecting the TEST-LOW position configures the ADC Borad for low speed operation by placing a logical "0" on the HI/LOW-SELECT signal

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line to the ADC Control Board. The toggle switch employed is an ALCO 20 5PA DPDT which has been configured to operate as a SP3T switch as shown in Figure 20 .

b. SAMPLE FREQUENCY Test Mode

The SAMPLE FREQUENCY test mode provides the op- tions of obtaining a single sample or sampling at a 100 kHz rate. The single sample mode of operation is selected by posi- tioning the SMPL FREQ toggle switch to the TEST-SINGLE position and depressing (and releasing) the TOGGLE momentary push but- ton switch. Depression of the TOGGLE switch causes a logical "0" to be applied to the input of a NAND gate contained in Ul, a 7400 quad NAND gate, resulting in a "1" to "0" transition. This transition leads to the generation of appropriate pulses on the ADC Board and results in a single conversion occurring. Releasing the TOGGLE switch applies a logical "0" to another NAND gate in Ul which causes a "0" to "1" transition and thereby restores the SAMPLE FREQUENCY line to its original condition. The interconnection of the two NAND gates into a debouncing configuration ensures that each depression of the TOGGLE switch results in a single transition (and conversion) . The TOGGLE pushbutton switch is an ALCO 205R DPDT momentary switch which is configured as shown in Figure 19. The 100 kHz sampling rate is selected by positioning the SMPL FREQ toggle switch to the TEST-100 position. The resultant 100 kHz sampling frequency is generated by U2, a 555 timer. The timing resistors have values of 6.8 kilohms and 1.8 kilohms while the charging capacitor has a rating of 1000 picofarads.

70

B

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1	—	1
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ALCO 205R and 205PA (Bottom View)

PIN NUMBER	SWITCH 1 (TOGGLE)		SWITCH 2 (SMPL FREQ)	SWITCH 3 (HI/LOW)
1		GROUND		pin 5	pin 5
2		Ul, pin 1		OUTPUT	OUTPUT
3		NC	*Sample Fre- quency	*HI/LOW SELECT
4		NC		Single Pulse	+5 Volts
5		Ul, pin 5		pin 1	pin 1
6		GROUND		100 kHz	GROUND
SWITCH	POSITIONS	SWITCH (SMPL ]	2 rREQ)	SWITCH 3 (HI/LOW)
	A	NORMAL	NORMAL
	B	TEST-	-LOW	TEST-	•100
	C	TEST-	-HIGH TEST-	•SINGLE

* - From ADC Control Board

Figure 20 Switch Configurations

71

The output of U2 is buffered by a HEX inverter contained in U3 to eliminate any ringing in the pulse train. Inasmuch as the Sample-Frequency clock signal is transmitted by coaxial cable, the output of the TOGGLE switch debouncer circuit and the 100 kHz pulse train are spplied to U4 , a 74S140 dual 50 ohm line driver, prior to being applied to the SMPL FREQ tog- gle switch inputs. Positioning this toggle switch to the NORMAL position restores control of the Sample-Frequency clock signal to the ADC Control Board. The SMPL FREQ toggle switch is an ALCO 20 5PA DPDT switch which was converted to operate SP3T as demonstrated in Figure 20.

72

IV. FUTURE DESIGN MODIFICATIONS

The review of manufacturers' literature during the compo- nent selection stage revealed two components which could be successfully incorporated into the Analog-to-Digital Control and Conversion subsystem. Unfortunately, these items were under development by their respective manufacturers and would not be commercially available during the development period of the prototype SSA. One of these components is a DIP pack- age sample-and-hold module which is being independently dev- eloped by TRW LSI Products and DATEL Systems, Inc. These units will be capable of speeds in excess of the 2 MHz re- quired by this subsystem. The other component of interest is an analog-to-digital converter presently being designed by DATEL Systems, Inc., which incorporates the operating fea- tures of the ADC-EH12B3 but is mounted in a DIP package. The redesign of the ADC Board to incorporate these two compon- ents (when available) would result in significant savings in cost and printed circuit (PC) board space. At the time of this writing, the final sampling frequencies to be employed in the production versions of the SSA had not been determined, Accordingly, all sample frequencies mentioned in this thesis (with the exception of the 2 MHz high-speed rate) are esti- mates of the final fixed values. Once the determination of the sampling frequencies has been finalized, the ADC Control Board is subject to modification through the removal of the

73

board mounted switches which control the generation of the sampling frequencies. The PC board modification to connect the load inputs of the divider components directly to appro- priate logical "1" or "0" values is a relatively minor change In addition to the obvious savings in board space, removal of these switches provides protection against the use of incor- rect sampling frequencies due to a switch being inadvertently left in the wrong position. These proposed modifications are easily implemented, represent no degradation in present sys- tem capabilities, and would allow the associated components to represent the technological state-of-the-art.

74

V. CONCLUSION

The Analog-to-Digital Control and Conversion subsystem of the prototype SATCOM Signal Analyzer has been designed and constructed. Inasmuch as the entire prototype system is in various stages of construction, the ADC Control Board and ADC Board (s) have not been exercised as components in an operating system. However, both boards and the ADC Test Box have been subjected to static and dynamic testing while mounted in the PLESSEY PM-1150/5 power chassis. The ADC Control Board and ADC Test Box have demonstrated the ability to control the ADC Board (s) in the various modes of operation The ADC Board successfully carries out analog-to-digital conversions in both the high-speed and low-speed modes. Based on these results, the ADC Control and Conversion sub- system is considered complete and operationally ready for integration into the prototype SATCOM Signal Analyzer.

75

APPENDIX A DUAL CHANNEL ANALOG TO DIGITAL CONVERSIONS THEORY

Dual channel analog-to-digital conversion is a technique whereby an incoming IF signal is downconverted to two base- band signals through mixing with two local oscillator sinu- soids. The local oscillator signals have equal magnitude and are phase related by 90 degrees. The mixing process results in the two baseband signals having a quadrature phase relationship. These signals are typically referred to as the "In-phase" and "Quadrature-phase" components. When these baseband signals are simultaneously sampled and analog- to-digital converted, numerical estimates of the "In-phase" and "Quadrature-phase" components are obtained. By allowing the "In-phase" value to represent the real value and the "Quadrature-phase" value to correspond to the imaginary val- ue, a complex data point may be derived (see Figure 21) . Application of this complex data point to FFT processing re- sults in an efficient use of the algorithm where all results are meaningful. This is in contrast to the single channel (real component) technique wherein the single (real) data point, when processed by an FFT algorithm produces a symme- tric output, half of which represents negative frequencies and is therefore redundant. The dual channel conversion method preserves all information within the bandpass of the IF signal (and therefore the RF signal) ; the zero frequency component in the resultant spectrum corresponds to the com- ponent of the RF signal which is at the same frequency as the

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local oscillator, as demonstrated in the following develop- ment :

IF Signal : x(t)

Local oscillator signal : cos qj t

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"Quadrature-phase" component : x(t) sin to t

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= x(t)

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= s(t) e

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Taking the Fourier Transform of y(t) results in

y(t)

= F

x(t) e

JV-T

= p (» - ooL;

78

APPENDIX B

This Appendix includes the major operating speicif cations of the DATEL SHM-UH sample-and-hold module, and the DATEL ADC-EH12B3 and TRW TDC-1001J analog-to-digital converters. It consists of Tables V through VII.

79

TABLE V DATEL SHM-UH SPECIFICATIONS

Case size Number of pins Power supplies Analog input range Input overvoltage Input impedance Gain Sample command

Settled output Output voltage range Maximum sampling rate

2" W x 2" L x .375" H

11

15 volts, + 15 volts

+ 5 volts

+ 10 volts

100 Megohms

+ 1

35 nanoseconds (+ 10 nanoseconds)

positive pulse 50 nanoseconds + 5 volts 10 MHz

80

TABLE VI DATEL ADC-EH12B3 SPECIFICATIONS

Case size Number of pins Power supplies Input voltage range Input overvoltage Input impedance Start convert

Outputs

Settled output

Maximum conversion rate

4" L x 2" W x .4" H

26

+ 5 volts, + 15 volts

+ 5 volts

+ 20 volts

1.15 kilohms

100 nanosecond (minimum) posi- tive pulse

12 parallel bits in two's com- plement or offset binary (both positive true)

2 microseconds (maximum)

500 kHz

81

TABLE VII TRW TDC-1001J SPECIFICATIONS

Case size Number of pins Power supplies Reference input Input voltage range Input overvoltage Input impedance Reference clock

Start convert

Output

Settled output

Maximum conversion rate

.3" W x .9" L x .4" H (DIP style)

18

+ 5 volts

- 0.5 volts

-0.5 volts to 0.0 volts

- 5 volts to +1 volt 25 kilohms

Pulse train at nine times the sampling rate with width of 20 nanoseconds (both minima)

50 nanosecond positive pulse (minimum)

Eight parallel bits in inverted offset binary format

Tenth reference pulse after conversion began

2.5 MHz

82

APPENDIX C

In order to optimize the accuracy of the digital outputs from the ADC Board, each of the analog-to-digital converters and the sample-and-hold module must be calibrated. In each case the static calibration of these devices is accomplished by adjusting either an internal or external resistance trim- pot. The calibration process requires the ADC Board to be mounted on standard PDP-11 extender boards with the bunched cable assembly from the ADC Control Board connected as in normal operations. Sample Frequency 2 (12.5 kHz) should be selected during the calibration process.

DATEL SHM-UH Sample-and-Hold Module

The DATEL SHM-UH contains an internal trimpot which is used to adjust the ZERO OFFSET of the device. Access to this trimpot is via an opening on the lower side of the case (as mounted on the ADC Board) between pins two and three. The analog input to the ADC Board must be terminated in a suitable load (50 ohm) to ensure a zero potential at the ana- log inputs to the SHM-UH. Connect a precision DC digital volt-meter to the analog outputs (pin 4 = High, pin 3 = Low) and adjust the trimpot to obtain a reading of 0.0 volts on the voltmeter.

DATEL ADC-EH12B3 Analog-to-Digital Converter

The DATEL ADC-EH12B3 has two adjustments (GAIN ADJUST and OFFSET ADJUST) which are performed through the use of two

83

external trimpots (TR3, TR4) . The OFFSET ADJUST calibration requires a precision DC voltage of -4.9988 volts to be applied to the analog input of the device. This is accomplished by the application of a precision DC voltage of -9.9976 volts to the analog input of the ADC Board. The serial version of the ADC-EH12B3 output may be observed on an oscilloscope by con- necting a probe to pin 4 (located at the top right corner of the mounted board). The EOC signal (pin l)may be used for oscilloscope display synchronization. Adjust the 200 ohm trim- pot (TR4) to obtain a pulse train which flickers between 0000 0000 0000 and 0000 0000 0001. The GAIN ADJUST calibration requires that a precision voltage of +4.9854 volts be applied to the analog input of the device (+9.9708 volts to the ana- log input of the board) . Observe the serial output of the device, as in the OFFSET ADJUST procedure, and adjust the 2 0 ohm trimpot (TR3) to obtain a pulse train which flickers between 1111 1111 1110 and 1111 1111 1111.

TRW TDC-1001J Analog-to-Digital Converter

The analog input voltage to the TRW TDC-1001J requires RANGE and OFFSET adjustment to be made to the output of the sample-and-hold module. This calibration requires the analog input to the ADC Board to be terminated in a zero potential (50 ohm) load. The RANGE adjustment is made by a twenty-to- one voltage (R13-R15) division of the analog output of the SHM-UH, which converts the + 5 volt range into a + .25 volt range. The OFFSET adjustment centers this reduced range at a center value of -.25 volts, obtained by a twenty-to-one

84

division of the -5 volt regulator output across a fixed 1 kilohm resistor (R13) and a 50 kilohm trimpot (TRl) . Con- nect a probe to Test Point 1 (located approximately in the center of the board) and adjust the trimpot until a reading of -.25 volts is obtained. The -.5 volt reference voltage required by the TDC-1001J (pin 13) is similarly obtained by a ten-to-one voltage division of the -5 volt signal across a fixed 1 kilohm resistor (R16) and another 50 kilohm trim- pot. A probe is connected to Test Point 2 (adjacent to Test Point 1) and the trimpot is adjusted to obtain a reading of -.5 volts at that point.

85

APPENDIX D

This appendix contains a listing of all pin and slot connections for the ADC Control Board and a typical ADC Board. The locations of the various connectors and slots may be determined from the component layout drawings (fig- ures 4 and 12) . Proper mounting of all ribbon connector mating connectors is facilitated by the etching of the num- ber "1" on each board adjacent to the proper location of pin 1 of the corresponding connectors. The PDP-11 backplane slots contain 18 pin connections which are lettered, from right to left, ABCDEFHJKLMNPRSTUV. The components on each board are mounted on side number 1; the reverse side is number 2. This appendix consists of Tables VIII and IX.

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96

APPENDIX E

This appendix contains a complete listing of all compon- ents mounted on the ADC and ADC Control Boards. Exact loca- tions of components (integrated circuits, connectors/ con- version modules, etc.) may be determined by reference to com- ponent layout diagrams (Figures 4 and 12) . Resistors and capacitors are generally located in close proximity to the components with which they appear in the board section sche- matics. This appendix consists of Tables X, XI, and XII.

97

TABLE X ADC CONTROL BOARD COMPONENT LIST (Page 1 of 1)

Component (s)

Ul, U4, U36

U2

U3, U5, U20-U27

U6 - U10 Ull - U15 U16 - U19 U28 - U35

U37 - U38

Rl

R2

R3

R4 - R3 5, R37, R3 8

R3 6

CI - C29, C32, C33

C30, C31

2N3945

J-l - J-4

J-5

J- 6

J-7

LED's (3)

H.H. Smith 6298 (2)

Description

7404 (Hex Inverter)

74S74 (Dual D Flip Flops)

74161 (Presettable Divide-By-16 Counter)

74S140 (Dual 50 Ohm Line Drivers)

74151 (One-of-Eight Multiplexer)

7420 (Dual Four Input NAND Gates)

76COA (Quad DIP Mounted SPDT Switches)

PRMA1A05C Reed Relays

50 Ohm Resistor (1/4W, 10%0

100 Ohm Resistor (l/4@, 10%)

2,2 kilohm Resistor (1/4W, 10%)

1.0 kilohm Resistors (1/4W, 10%)

330 ohm Resistor (1/4W, 10%)

.01 microfarad (50V) Ceramic Capacitors (DIP Style)

10 microfarad (50V) Electrolytic Capacitors

High Power NPN Transistor

Cannon DAM 7W25A Connectors

Cannon DAM 3W3S Connector

Ansley 609-615M Mating Connector

SMA Bulkhead Fitting

Unidirectional

Board Extractors

98

TABLE XI ADC BOARD COMPONENT LIST (Page 1 of 2)

Component (s)

DATEL SHM-UH
DATEL ADC-EH12B3
TRW	TDC-1001J
Ul,	U2, U19, U21
U3
04,	U20, U22
U5
U6
U7
U8 -	• U14
U15	- U17
U18
VI
V2
TR1,	TR2
TR3
TR4
Rl -	■ R6, R13, R14, R16
R7 -	• RIO
Rll,	R12
R15
R17,	R2 2
R18
R19
R20,	R21
CI - C18, C22, C24, C2 C30, C32, C33, C37-4
C19
C20,	C21

Description

Sample-and-Hold Module

Low-Speed ADC Module

High-Speed ADC Module

74121 (One Shot Multivibrator)

74S140 (Dual 50 Ohm Line Driver)

7404 (Hex Inverters)

7432 (Quad Two Input OR Gates)

LM318 Operational Amplifier

PRMA1A05C Reed Relay

74175 (Quad D Latches)

74157 (Quad One-of-Two Multi- plexer)

74107 (Dual J-K Flip Flops)

LM320T-5 (-5 V Regulator)

LM340-5 (+5 V Regulator)

70Y503 (50 Kilohm Trimpots)

8 9PR20 (20 Ohm Trimpot)

89PR200 (200 Ohm Trimpot)

1 kilohm Resistors (1/4W, 10%)

10 kilohm Resistors (1/4W, 10%)

1.0 kilohm Resistors (1/4W, 5%)

18 kilohm Resistor (1/4W, 10%)

2.7 kilohm Resistor (1/4W, 10%)

100 ohm Resistor (1/2W, 10%)

3.3 kilohm Resistor (1/4W, 10%)

50 ohm Resistors (1/4W, 10%)

.01 microfarad Ceramic Capacitors (DIP Style)

25 microfarad (1KV) Ceramic Capacitor

82 microfarad (1KV) Ceramic Capacitor

99

TABLE XI ADC BOARD COMPONENT LIST (Page 1 of 2)

C23

C25

C27

C28

C29

C31, C34-C36

J-l J- 2

J-3

H.H. Smith 6298(2)

.2 microfarad (16V) Ceramic Capacitor

2.2 microfarad (35V) Tantalum Capacitor

.22 microfarad (35V) Tantalum Capacitor

5 microfarad (1KV) Ceramic Capacitor

68 picofarad (1KV) Ceramic Capacitor

10 microfarad (50V) Electrolytic Capacitors

CANNON DAM-TW25A Connector

ANSLEY 609-3415M Mating Connec- tor

SMA Bulkhead Fitting

Board Extractors

100

TABLE XII ADC TEST BOX COMPONENT LIST

Component (s) Description

7400 (Quad NAND Gates)

555 (Timer)

7404 (HEX Inverters)

74S140 (Dual 50 Ohm Line Driver)

22 kilohm Resistors (1/4W, 10%)

6.8 kilohm Resistor (1/4W, 10%)

1.8 kilohm Resistor (1/4W, 10%)

1.0 kilohm Resistor (1/4W, 10%)

.01 microfarad Ceramic Capacitor (DIP Style)

C5 .001 microfarad (1KV) Ceramic

Capacitor

J-l CANNON DAM-7W2 5A Connector

SW1 ALCO 205R DPDT (Momentary) Switch

SW2, SW3 ALCO 205PA DPDT Switch

Ul
U2 TT*5
U J U4
Rl,	R2
R3
R4
R5,	R6
CI ■	- C4

101

LIST OF REFERENCES

1. Naval Postgraduate School Report 620L76105, Deck Boxes

for UHF SATCOM Radio Frequency Interference, by G. B. Parker and J. E. Ohlson, October 1976.

2. Naval Postgraduate School Report 6 20L76108, Instrumen-

tation Package for Measurement of Shipboard RFT, by A. R. Shuff and J. E. Ohlson, October 1976.

3. Naval Postgraduate School Report 620L7 6103, Shipboard

Radio Frequency Interference in UHF Satellite Com- munications , by T. C. Landry and J. E. Ohlson (CON- FIDENTIAL) , October 1976.

4. Naval Postgraduate School Report 62-7 8-001, Digital Con-

trol and Processing for a Satellite Communications Monitoring System, by G. W. Bohannon, January 1978.

5. Langston, M. J., Data Acquisition Unit for a SATCOM

Signal Analyzer, M.S.E.E. Thesis, Naval Postgraduate School, June 1978.

6. Mead, R. R. , Digital Control and Interfacing for a High

Speed Satellite Communications Signal Processor, M.S. E.E. Thesis, Naval Postgraduate School September 1978.

7. Forgy, J. M. , Long Term Stability and Drift Measurement

of GAPFILLER's Onboard Oscillator, M.S.E.E. Thesis, Naval Postgraduate School, December 1978.

8. DATEL Systems Inc., DATEL Sample and Hold Module Speci-

fications, Bulletin SUHBLL050L, Ultra High Speed Sam- ple and Hold Model SHM-UH, January 197 5.

9. DATEL Systems Inc., DATEL Analog-to-Digital Conversion

Module Specifications, Bulletin EHDANL0606, Ultra Fast 12 Bit Analog-to-Digital Converter Model ADC-EH12133, June 1976.

10. TRW LSI Products, TRW Analog-to-Digital Conversion Module,

Preliminary Bulletin, A/D Converters Models TDC-1001J and TDC-1002J, July 197T;

11. Analog Devices Inc., Analog-Digital Conversion Handbook,

1972.

102

INITIAL DISTRIBUTION LIST

No. of Copies

1. Commander 8 (Attn: E. L. Warden, PME-106-112A)

Naval Electronic Systems Command Department of the Navy Washington, D.C. 20360

2. Commander 1 (Attn: W. C. Willis, PME-106-11)

Naval Electronic Systems Command Department of the Navy Washington, D.C. 20360

3 . Commander 1 (Attn: W. R. Coffman, PME-106-16)

Naval Electronic Systems Command Department of the Navy Washington, D.C. 20360

4 . Library 2 Naval Postgraduate School

Monterey, California 93940

5. Office of Research Administration (012A) 1 Naval Postgraduate School

Monterey, California 93940

6. Professor John E. Ohlson 20 Code 620L

Naval Postgraduate School Monterey, California 93940

7. Commander 1 (Attn: LT Gary W. Bohannon, G60)

Naval Security Group

3810 Nebraska Avenue, N.W.

Washington, D.C. 20390

8. Commander 1 (Attn: Robert S. Trible, 0252)

Naval Electronic Systems Engineering Activity (NESEA) Patuxent River, Maryland 20670

103

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